Ricerc@Sapienza

Approximate DRAMs are DRAM memories where energy saving techniques have been implemented by trading off bit-cell error rate with power consumption. They are considered part of the building blocks in the larger area of approximate computing. Relaxing refresh rate has been proposed as an interesting solution to achieve better efficiency at the expense of rising error rate. However, some works have demonstrated that much better results are achieved if at word-level some bits are retained without errors (i.e.

This paper presents the design and the implementation of a fully combinatorial floating point unit (FPU). The FPU can be reconfigured at implementation time in order to use an arbitrary number of bits for the mantissa and exponent, and it can be synthesized in order to support all IEEE-754 compliant FP formats but also non-standard FP formats, exploring the trade-off between precision (mantissa field), dynamic range (exponent field) and physical resources.