Skip to main content

Ricerc@Sapienza

Home
Login

Home
CMOS technology
2017
Risultati ricerca pubblicazioni

Risultati ricerca pubblicazioni

The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture

pubblicato su: AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS - 2017

Stornelli V., Pantoli Leonardo, Ferri G., Liberati L., Centurelli Francesco, Monsurro' Pietro, Trifiletti Alessandro

Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications

pubblicato su: IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING - 2017

Bellizia Davide, Bongiovanni Simone, Monsurro' Pietro, Trifiletti Alessandro, Scotti Giuseppe

Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies

pubblicato su: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS - 2017

Scotti Giuseppe, Bellizia Davide, Trifiletti Alessandro, Palumbo Gaetano

CATALOGO IRIS SAPIENZA

Anno

(-) Remove 2017 filter 2017

Tipo pubblicazione

01 Pubblicazione su rivista (3) Apply 01 Pubblicazione su rivista filter

Rivista

AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS (1) Apply AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS filter
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING (1) Apply IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING filter
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (1) Apply IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS filter

Book

Keywords

(-) Remove CMOS technology filter CMOS technology
Adaptive biasing (1) Apply Adaptive biasing filter
Amplifiers (electronic) (1) Apply Amplifiers (electronic) filter
Clocks (1) Apply Clocks filter
CMOS integrated circuits (1) Apply CMOS integrated circuits filter
Conveyors (1) Apply Conveyors filter
cryptographic circuits (1) Apply cryptographic circuits filter
cryptography (1) Apply cryptography filter
Current conveyors (1) Apply Current conveyors filter
current mode logic (CML) D-latch (1) Apply current mode logic (CML) D-latch filter
D flip-flop (DFF) (1) Apply D flip-flop (DFF) filter
Electrical and Electronic Engineering (1) Apply Electrical and Electronic Engineering filter
Inverters (1) Apply Inverters filter
Latches (1) Apply Latches filter
logic gates (1) Apply logic gates filter
Low power architecture (1) Apply Low power architecture filter
low voltage (1) Apply low voltage filter
nanometer CMOS (1) Apply nanometer CMOS filter
nanometer CMOS. (1) Apply nanometer CMOS. filter
power analysis attacks (1) Apply power analysis attacks filter
power demand (1) Apply power demand filter
semiconductor device modeling (1) Apply semiconductor device modeling filter
side-channel attacks (1) Apply side-channel attacks filter
Software (1) Apply Software filter
standards (1) Apply standards filter
static power (1) Apply static power filter
topology (1) Apply topology filter
Transistors (1) Apply Transistors filter

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma