Skip to main content

Ricerc@Sapienza

Home
Login

Home
cryptography
dual-rail logic
Risultati ricerca pubblicazioni

Risultati ricerca pubblicazioni

TEL logic style as a countermeasure against side-channel attacks: secure cells library in 65nm CMOS and experimental results

pubblicato su: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS - 2018

Bellizia D., Scotti G., Trifiletti A.

CATALOGO IRIS SAPIENZA

Anno

2018 (1) Apply 2018 filter

Tipo pubblicazione

01 Pubblicazione su rivista (1) Apply 01 Pubblicazione su rivista filter

Rivista

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (1) Apply IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS filter

Book

Keywords

(-) Remove cryptography filter cryptography
(-) Remove dual-rail logic filter dual-rail logic
delay-based dual-rail pre-charge logic (DDPL) (1) Apply delay-based dual-rail pre-charge logic (DDPL) filter
power analysis attacks (PAAs) (1) Apply power analysis attacks (PAAs) filter
sense amplifier-based logic (SABL) (1) Apply sense amplifier-based logic (SABL) filter

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma