Skip to main content
Ricerc@Sapienza
Toggle navigation
Home
Login
Home
mauro.olivieri@uniroma1.it
Mauro Olivieri
Professore Associato
Struttura:
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI
E-mail:
mauro.olivieri@uniroma1.it
Pagina istituzionale corsi di laurea
Curriculum Sapienza
Publications
Title
Published on
Year
Customizable vector acceleration in extreme-edge computing: A risc-v software/hardware architecture study on VGG-16 implementation
ELECTRONICS
2021
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores
IEEE MICRO
2021
The Italian research on HPC key technologies across EuroHPC
Proceedings of the 18th ACM International Conference on Computing Frontiers 2021, CF 2021
2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
34rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
2021
A low-voltage class-AB OTA exploiting adaptive biasing
AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
2020
Quality aware selective ECC for approximate DRAM
Applications in Electronics Pervading Industry, Environment and Society APPLEPIES 2019
2020
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer
Lecture Notes in Electrical Engineering
2020
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
Lecture Notes in Electrical Engineering
2020
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS
2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020
2020
An fpga-based risc-v computer architecture orbital laboratory on a pocketqube satellite
Advances in the Astronautical Sciences
2020
Full system emulation of approximate memory platforms with AppropinQuo
JOURNAL OF LOW POWER ELECTRONICS
2019
Approximate memory support for Linux early allocators in ARM architectures
Applications in Electronics Pervading Industry, Environment and Society
2019
Synthesis time reconfigurable floating point unit for transprecision computing
Applications in Electronics Pervading Industry, Environment and Society
2019
The international race towards Exascale in Europe
CCF TRANSACTIONS ON HIGH PERFORMANCE COMPUTING
2019
LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits
Communications in Computer and Information Science
2019
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
Lecture Notes in Electrical Engineering
2019
Dosimetric characterization of an irradiation set-up for electronic components testing at the TOP-IMPLART proton linear accelerator
Proceedings of RADECS 2019, Montpellier 17-20 September 2019
2019
Quality aware approximate memory in RISC-V Linux Kernel
PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings
2019
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique
Lecture Notes in Electrical Engineering
2018
« first
< previous
1
2
3
next >
last »
ERC
PE6_1
PE7_5
KET
Big data & computing
Micro/nano electronics & photonics
Interessi di ricerca
Keywords
digitale
microelettronica
microprocessors
Progetti di Ricerca
Progetto di unita' di accelerazione vettoriale per processori embedded in ambito edge computing Design of vector processing units for embedded processor in edge computing
Near-sensor processors for AI-configured Internet-of-Things nodes
Design of special-purpose microprocessors for High-Altitude Pseudo-Satellite (HAPS) drones operating in harsh conditions.
© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma