Ricerc@Sapienza

The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without affecting the differential-mode behavior; simulations of a sample- A nd-hold exploiting the proposed OTA topology are also presented.

A class-AB OTA (operational transconductance amplifier) topology
with rail-to-rail input common-mode range is proposed for application
in very low-voltage applications. High efficiency is achieved by
reusing transistors both for class-AB operation and for mirroring the
output currents, and a threshold lowering technique is applied to
allow supply voltages less than two threshold voltages. Simulations
in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply
voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero.

We present a low voltage approach to design an adaptive bias circuit for a class-AB input stage, and exploit it to design a fully-differential 0.6 V class-AB symmetrical OTA that also features cascode dynamic biasing and a class-AB CMFB circuit. Simulations in 0.13 μm CMOS technology show a 42x increase of the bias current when signal is applied, that yields a faster settling time with respect to a class-A OTA designed with the same static current.