CMOS technology

A revision of the theory of THz detection by MOSFET in the light of the self-mixing model

CMOS technology has been extensively used for the realization of image sensors at Terahertz frequencies. The explanation of its strong efficiency was usually given invoking a mechanism described by the plasma wave detection theory. This model predicts that, when a high frequency potential is applied between gate and source electrodes of a MOSFET, oscillations of the 2D electron gas, located in the inversion layer, converts THz radiation into a DC voltage.

Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propagation delay derived for both low-voltage topologies.

The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture

We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35 um CMOS technology, an extra current flows into the circuit only when an input voltage variation occurs (through the adaptive biasing technique), so improving the transient response speed without a substantial increase of the average power consumption. Simulation results confirm the expected theoretical considerations.

Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications

In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology.

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