Ricerc@Sapienza

The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and better numerical properties. We propose a VHDL implementation that has been successfully implemented on a Xilinx Virtex-7 FPGA. The FWL RLS algorithm has a complexity of L2 + O(L) products, instead of 1.5L2 O(L) as in conventional RLS algorithms. Because it removes all matrix operations, separating an L input vector problem into L separate scalar problems, it is stable and often faster in fixed-point arithmetic than conventional RLS.

Segment routing (SR) is a new routing paradigm to provide traffic engineering (TE) capabilities in an IP network. The main feature of SR is that no signaling protocols are needed, since extensions of the interior gateway protocol routing protocols are used. Despite the benefit that SR brings, introducing a new technology into an operational network presents many difficulties. In particular, the network operators consider both capital expenditure and performance degradation as drawbacks for the deployment of the new technology; for this reason, an incremental approach is preferred.