Ricerc@Sapienza

We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35 um CMOS technology, an extra current flows into the circuit only when an input voltage variation occurs (through the adaptive biasing technique), so improving the transient response speed without a substantial increase of the average power consumption. Simulation results confirm the expected theoretical considerations.

A 4th-order Butterworth class-AB current-mode low-pass filter is proposed, based on second-generation Current Conveyors (CCII). Class-AB operation allows high-power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class-AB output buffer with error amplifiers: this topology is known to be sensitive to mismatch errors, which cause offsets in the error amplifiers, affecting the biasing current of the stage. This problem is solved via a control loop, which compensates the effect of mismatches.