Ricerc@Sapienza

In this paper, a novel modeling framework is proposed to quickly estimate the delay variability of logic paths due to random variations, and evaluate the related design margin. The analysis shows that the popular fan-out-of-4 metric F04 can capture the impact of technology and voltage on the delay variations of logic paths. Once those contributions are isolated, the impact of random variations on standard cells' delay is accounted for by means of cell-specific coefficients that are evaluated in a preliminary library characterization phase.

In this paper, a novel framework is introduced to estimate the max-delay variability in logic paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of the additional cycle time margin imposed by random (local) variations. The framework provides the designer with a deep insight into the main variability contributions, and the improvements allowed by prospective design modifications (e.g., logic restructuring and cell up-sizing). The proposed framework is applicable to a wide voltage range, from sub-threshold to nominal.