Ricerc@Sapienza

In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed approach allows a minimum power supply equal to the one of a MCML inverter and we show analytically the advantages in terms of speed and power consumption against the conventional implementation.

This paper presents the design of a novel low-voltage high-speed D-latch circuit suitable for nanometer CMOS technologies. The proposed topology is compared against the low-voltage triple-tail D-latch and its advantages are demonstrated both by simulations, under different performance/power consumption tradeoffs with a 40-nm CMOS technology, and theoretically, thanks to a simple model of the propagation delay derived for both low-voltage topologies.

This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art.

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐compensated amplifier employing multipath to remove the positive zero.

We present a low voltage approach to design an adaptive bias circuit for a class-AB input stage, and exploit it to design a fully-differential 0.6 V class-AB symmetrical OTA that also features cascode dynamic biasing and a class-AB CMFB circuit. Simulations in 0.13 μm CMOS technology show a 42x increase of the bias current when signal is applied, that yields a faster settling time with respect to a class-A OTA designed with the same static current.

An innovative low-voltage low-power complementary metal-oxide-semiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate-driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch. The solution is also exploited in a rail-to-rail high-performance single-stage cascode operational transconductance amplifier (OTA).

This brief presents ultra low-voltage CML D-latch and D-Flip-Flop (DFF) topologies in deeply scaled CMOS technologies, able to operate at a supply voltage as low as 0.5 V (no other CML DFFs are able to operate at such a low supply voltage). The topology is based on a modified version of the Folded D-Latch, recently proposed by the authors. In this brief a detailed analysis on the minimum supply voltage allowed by the proposed topologies and a comparison with the one of the other low voltage topologies is also included.