Ricerc@Sapienza

This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art.

This brief presents ultra low-voltage CML D-latch and D-Flip-Flop (DFF) topologies in deeply scaled CMOS technologies, able to operate at a supply voltage as low as 0.5 V (no other CML DFFs are able to operate at such a low supply voltage). The topology is based on a modified version of the Folded D-Latch, recently proposed by the authors. In this brief a detailed analysis on the minimum supply voltage allowed by the proposed topologies and a comparison with the one of the other low voltage topologies is also included.