Ricerc@Sapienza

In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed approach allows a minimum power supply equal to the one of a MCML inverter and we show analytically the advantages in terms of speed and power consumption against the conventional implementation.

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter.

The static power consumption in modern integrated circuits has become a critical standpoint in side-channel analysis. As it has been widely demonstrated in the technical literature, it is possible to extract secret information from a cryptographic circuit by means of static current measurements. Static and dynamic power analysis require different measurement procedures, due to physical reasons.

In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology.

This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art.

In this paper we present propagation delay models for MCML gates with resistor- or triode-PMOS-based output I–V conversion. The dependence of the parasitic capacitance of triode PMOS devices is accurately evaluated for the first time in the literature. The proposed models are able to accurately predict the propagation delay as a function of the bias current ISS in different design scenarios which require different tradeoffs between speed, area and power efficiency.

This brief presents ultra low-voltage CML D-latch and D-Flip-Flop (DFF) topologies in deeply scaled CMOS technologies, able to operate at a supply voltage as low as 0.5 V (no other CML DFFs are able to operate at such a low supply voltage). The topology is based on a modified version of the Folded D-Latch, recently proposed by the authors. In this brief a detailed analysis on the minimum supply voltage allowed by the proposed topologies and a comparison with the one of the other low voltage topologies is also included.