TEL logic style as a countermeasure against side-channel attacks: secure cells library in 65nm CMOS and experimental results
This paper presents experimental results on a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions. The proposed logic family is based on the time enclosed logic (TEL) encoding and can be viewed as an improvement of the delay based dual rail pre-charge logic (DDPL) logic style. The DDPL logic gates have been redesigned to avoid the early evaluation effect and to reduce area and power consumption. A library of TEL secure gates and flip-flops has been implemented in a 65 nm CMOS process.