The static power consumption in modern integrated circuits has become a critical standpoint in side-channel analysis. As it has been widely demonstrated in the technical literature, it is possible to extract secret information from a cryptographic circuit by means of static current measurements. Static and dynamic power analysis require different measurement procedures, due to physical reasons.
In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology.
Commodity HardWare (CHW) is currently used in the Internet to deploy large data centers or small computing nodes. Moreover, CHW will be also used to deploy future telecommunication networks, thanks to the adoption of the forthcoming network softwarization paradigm. In this context, CHW machines can be put in Active Mode (AM) or in Sleep Mode (SM) several times per day, based on the traffic requirements from users. However, the transitions between the power states may introduce fatigue effects, which may increase the CHW maintenance costs.
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