A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4s metric
In this paper, a novel framework is introduced to estimate the max-delay variability in logic paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of the additional cycle time margin imposed by random (local) variations. The framework provides the designer with a deep insight into the main variability contributions, and the improvements allowed by prospective design modifications (e.g., logic restructuring and cell up-sizing). The proposed framework is applicable to a wide voltage range, from sub-threshold to nominal.