Ricerc@Sapienza

Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution to maximize the pipeline utilization, when it comes to executing parallel applications, as different threads operate different instruction processing phases in the same cycle. In this study, we expand the target applications of an IMT microarchitecture by introducing an efficient yet handy special-purpose mathematics engine, operating on local scratchpad memories that give low latency and wide data-bus access.

Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running multiple control threads. Such architecture scheme fits one of the main target application domain of the RISC-V instruction set. We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for IoT applications. The latter feature is a novel contribution in this application domain.