semiconductor device modeling

New insight on terahertz rectification in a metal–oxide–semiconductor field-effect transistor structure

The use of a metal–oxide–semiconductor field-effect transistor (MOS-FET) permits the rectification of electromagnetic radiation by employing integrated circuit technology. However, obtaining a high-efficiency rectification device requires the assessment of a physical model capable of providing a qualitative and quantitative explanation of the processes involved. For a long time, high-frequency detection based on MOS technology was explained using plasma wave detection theory.

Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications

In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology.

Self-mixing model of terahertz rectification in a metal oxide semiconductor capacitance

Metal oxide semiconductor (MOS) capacitance within field effect transistors are of great interest in terahertz (THz) imaging, as they permit high-sensitivity, high-resolution detection of chemical species and images using integrated circuit technology. High-frequency detection based on MOS technology has long been justified using a mechanism described by the plasma wave detection theory. The present study introduces a new interpretation of this effect based on the self-mixing process that occurs in the field effect depletion region, rather than that within the channel of the transistor.

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