Ricerc@Sapienza

The occurrence of voltage noise in digital circuits has been typically associated to logic errors. The noise exposure of nano-scale circuits, associated to process variability, makes it interesting to explore the impact of input noise voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised. This work proposes a simple yet effective characterization model to characterize the resulting shift in static energy consumption.

Static power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level leakage current estimation technique relying on an internal node voltage-based model. The model is implemented in the form of VHDL packages. By utilizing the capability of the model, the behavior of major leakage component has been analyzed separately for FinFET technology scaling over single- and multi-stage digital standard cells.