Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications
In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology.