Optimal pipeline stage balancing in the presence of large isolated interconnect delay
01 Pubblicazione su rivista
Olivieri Mauro, Menichelli Francesco, Mastrandrea Antonio
DOI: 10.1049/el.2016.4262
ISSN: 0013-5194
Pipelining a combinational logic data-path without introducing pipeline stage delay imbalance is a key requirement for efficient digital processing. Balanced pipelining is easily achieved by simple logical effort optimisation when the interconnect and fan-out delay overhead is small and homogeneously distributed. When the target microarchitecture design includes isolated long interconnects, such as buses, optimal pipeline stage balancing becomes a tricky problem. This work formalises the solution based on the logical effort paradigm and evidences its advantage with respect to a heuristic approach.
combinational circuits combinational logic data-path digital processing fan-out delay overhead heuristic approach Integrated circuit interconnections large isolated interconnect delay optimal pipeline stage balancing optimisation pipeline processing pipeline stage delay imbalance simple logical effort optimisation