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nanometer CMOS
2020
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Delay models and design guidelines for MCML gates with resistor or PMOS load

pubblicato su: MICROELECTRONICS JOURNAL - 2020

Centurelli F., Scotti G., Trifiletti A., Palumbo G.

A novel 0.5 v MCML D-flip-flop topology exploiting forward body bias threshold lowering

pubblicato su: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS - 2020

Scotti G., Trifiletti A., Palumbo G.

A multi-folded MCML for ultra-low-voltage high-performance in deeply scaled CMOS

pubblicato su: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS - 2020

Palumbo G., Scotti G.

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(-) Remove 2020 filter 2020

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01 Pubblicazione su rivista (3) Apply 01 Pubblicazione su rivista filter

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS (1) Apply IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS filter
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS (1) Apply IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS filter
MICROELECTRONICS JOURNAL (1) Apply MICROELECTRONICS JOURNAL filter

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Keywords

(-) Remove nanometer CMOS filter nanometer CMOS
current mode logic (CML) (2) Apply current mode logic (CML) filter
low voltage (2) Apply low voltage filter
D-flip-flop (1) Apply D-flip-flop filter
delay model (1) Apply delay model filter
logic circuits (1) Apply logic circuits filter
logic design (1) Apply logic design filter
MCML (1) Apply MCML filter
SCL (1) Apply SCL filter

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