Scaling the Metal Oxide Semiconductor (MOS) transistor dimensions down to the nanoscale and increasing the density of bits in an integrated Complementary MOS (CMOS) chip are mainly led by an extraordinary improvement of chip performance and the consequent economic revenues for semiconductor industries. Unfortunately, scaling the MOS size also causes a variety of drawbacks, degrading the transistor and circuit reliability. These are mainly due to local increase of the electric field in the transistor, creation of new traps in the gate oxide and transient phenomena related to capture and release of free carriers in the defect sites. The time-to-failure is the lifetime before a certain percentage degradation of the electrical behaviour of the transistor. It is a key feature of the technology node monitored by the semiconductor industries before releasing the product to the market. Among others, the instability of the threshold voltage is one of the most critical effect of the transistor reliability degradation, since alters the switch-on and switch-off conditions of the transistor. In this project, we propose to make systematic measurements of the threshold voltage instability during and after stress and to develop an analytical model able to explain the physical mechanisms involved and the role of the different types of traps. The ultimate goal of the project is to predict the transistor time-to-failure. Samples will be stressed at various temperatures and voltages, after which the threshold voltage will be measured. However, during the delay time after the end of the stress before the measurement a partial recovery of the threshold voltage occurs, which alters the value of the measurement, thus introducing an error in the calculation of the time-to-failure. An accurate model also of the recovery will be necessary to correct that error and to extrapolate the true value of the time-to-failure of the transistor.
This activity research will hopefully bring to advancement of knowledge respect to the state-of-art for two reasons: 1) for the first time, a comprehensive analytical model of all the physical mechanisms ruling the kinetics of traps during the NBTI stress and the following recovery will be proposed; 2) the analytical modeling of the trap kinetics during the delay time after the end of the stress will allow to write a correction function to be applied to the measurements. This would be the first time that such a correction is analytical and not empirical.
As for reason 1), innovation respect to literature lies in the fact that, in addition to the interface traps creation always considered as the ONLY responsible of threshold voltage instability, during NBTI stress we will write analytical equations also for the creation of new bulk oxide traps and the hole trapping into pre-existing border traps. In the past, the bulk traps were accounted for with empirical laws, whereas we are confident to be able to describe the whole experiment with analytical laws. The analytical approach allows to develop a physically-based predictive tool, and not only a descriptive tool. This takes us to the second reason of innovation and knowledge progression.
As for reason 2), having the analytical model of the threshold voltage instability during the time delay allows to correct the measurement for the partial recovery and therefore to monitor the exact variation of that electrical parameter. This is a great advancement respect to the state-of-art since would enable to calculate the real time-to-failure of the transistor in that technology node.