Mauro Olivieri

Pubblicazioni

Titolo Pubblicato in Anno
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme IEEE TRANSACTIONS ON COMPUTERS 2024
AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs Proceedings of the International Joint Conference on Neural Networks 2024
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems IEEE ACCESS 2024
A RISC-V fault-tolerant soft-processor based on full/partial heterogeneous dual-core protection IEEE ACCESS 2024
Heterogeneous tightly-coupled dual core architecture against single event effects Lecture Notes in Electrical Engineering 2024
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design Lecture Notes in Electrical Engineering 2024
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach Lecture Notes in Electrical Engineering 2024
Contextual bandits algorithms for reconfigurable hardware accelerators Lecture Notes in Electrical Engineering 2023
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor 2023
Improving SET fault resilience by exploiting buffered DMR microarchitecture SIE 2022. Proceedings of SIE 2022 2023
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy SIE 2023: Proceedings of SIE 2023 2023
Fault-tolerant hardware acceleration for high-performance edge-computing nodes ELECTRONICS 2023
Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) 2023
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices International Symposium on High-Performance Computer Architecture (HPCA) 2023
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2023
FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit MICROPROCESSORS AND MICROSYSTEMS 2023
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration Conference on Ph.D Research in Microelectronics and Electronics (PRIME) 2022
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS 2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors IEEE ACCESS 2022
BiSon-e: A Lightweight and High-Performance Accelerator for Narrow Integer Linear Algebra Computing on the Edge International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS 2022

ERC

  • PE6_1
  • PE7_5

KET

  • Big data & computing
  • Micro/nano electronics & photonics

Interessi di ricerca

Digital VLSI design; Microprocessor design; Hadrware accelerators; Fault-tolerant processors; RISC-V; Vector computing; Edge computing.

Keywords

digitale
microelettronica
microprocessors

Progetti di Ricerca

Laboratori di ricerca

Laboratori Sistemi Digitali

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