Ricerc@Sapienza

We propose here an implementation of 2D hierarchical clustering tailored for power constrained and low-precision hardware. In many application fields such as smart sensor networks, having low computational capacity is mandatory for energy saving purposes. In this context, we aim to deploy a specific constrained hardware solution, using a parallel architecture with a low number of bits. The effectiveness of the proposed approach is corroborated by testing it on well-known 2D clustering datasets.

In this paper we propose a novel hardware implementation for a bidimensional unconstrained hierarchical clustering method, based on fuzzy logic and membership functions. Unlike classical clustering approaches, our work is based on an advanced algorithm that shows an intrinsic parallelism. Such parallelism can be exploited to design an efficient hardware implementation suitable for low-resources, low-power and highcomputational demanding applications like smart-sensors and IoT devices. We validated our design by an extensive simulation campaign on well known 2D clustering datasets.

Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution to maximize the pipeline utilization, when it comes to executing parallel applications, as different threads operate different instruction processing phases in the same cycle. In this study, we expand the target applications of an IMT microarchitecture by introducing an efficient yet handy special-purpose mathematics engine, operating on local scratchpad memories that give low latency and wide data-bus access.