Ricerc@Sapienza

This letter describes a 16 × 8-pixel array based on single-photon avalanche diodes (SPADs) optimized for the readout of a tracking detector based on plastic scintillation fibers targeting ultra-fast neutrons. Each pixel of 125 × 250 μm2 size contains 30 SPADs,an 80-ps 10-b time-to-digital converter (TDC),a 5-b intensity counter,a finite state machine (FSM) that manages the recording of data and a three-word-deep FIFO memory for parallel acquisition and readout,achieving 32.1% pixel fill factor.

Scintillation mechanisms in gases offer the possibility of an optical readout of micropattern gas detectors. This approach takes advantage of the large progress achieved in last years in the performance of the photosensors, opening the way to the realization of high granularity and very sensitive particle trackers. In this paper, the features of a triple-GEM structure filled with a He/CF4 (60/40) mixture and readout by a CMOS sensor are described.

The MOnitor for Neutron Dose in hadrOntherapy (MONDO) project addresses the technical challenges posed by a neutron tracker detector aiming for a high detection efficiency and a good backtracking precision. The project aims to develop a tracking device capable of fully reconstructing the four momen- tum of fast and ultrafast secondary neutrons produced, e.g., in particle therapy (PT) treatments or in other physical processes.

GEM-based detectors had a noticeable development
in last years and have successfully been employed in different
fields from High Energy Physics to imaging applications. Light
production associated to the electron multiplication allows to
perform an optical readout of these devices. The big progress
achieved in CMOS-based photo-sensors makes possible to develop
a high sensitivity, high granularity and low noise readout. In this
paper we present the results obtained by reading out the light
produced by a triple-GEM structure by means o

In this paper, a novel modeling framework is proposed to quickly estimate the delay variability of logic paths due to random variations, and evaluate the related design margin. The analysis shows that the popular fan-out-of-4 metric F04 can capture the impact of technology and voltage on the delay variations of logic paths. Once those contributions are isolated, the impact of random variations on standard cells' delay is accounted for by means of cell-specific coefficients that are evaluated in a preliminary library characterization phase.

Security of sensible data for ultraconstrained IoT smart devices is one of the most challenging task in modern design. The needs of CPA-resistant cryptographic devices has to deal with the demanding requirements of small area and small impact on the overall power consumption. In this work, a novel current-mode feedback suppressor as on-chip analog-level CPA countermeasure is proposed. It aims to suppress differences in power consumption due to data-dependency of CMOS cryptographic devices, in order to counteract CPA attacks.

Latest nanometer CMOS technology nodes have highlighted new issues in security of cryptographic hardware implementations. The constant growth of the static power consumption has led to a new class of side-channel attacks. Common attacks exploiting static power use an univariate approach to recover information from cryptographic engines. In our work, a multivariate approach based on information theoretic security metrics is presented. The temperature-dependence helps to exploit more information leakage from the hardware implementation.

Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs.

An innovative low-voltage low-power complementary metal-oxide-semiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate-driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch. The solution is also exploited in a rail-to-rail high-performance single-stage cascode operational transconductance amplifier (OTA).

Silicon nanowires grown by the VLS mechanism resulted as efficient chemical and biological sensors as field effect transistors, nevertheless up to date a key point is the integration of the nanostructure in actual integrated circuit. The basic requirement appears the possibility to perform the deposition at low temperature, directly on the backside of the already finished integrated circuit. This would combine the high chemical sensitivity of the nanowires with the sensitivity, the elaboration capability, and the low production cost of CMOS technology.