Ricerc@Sapienza

We present a new solid state rectifier, compatible with CMOS integrated circuit, suitable to direct conversion of terahertz radiation, at room temperature. The structure creates a rectenna, consists in a truncated conical helix extruded from a planar spiral and connected to a nanometric metallic whisker at one of its edges. The whisker reaches the gate of a MOS-FET transistor. Rectification can be obtained by the self-mixing effect occurring into the plasma waves generate underneath the gate. The proposed solution is easy to integrate with existing imaging systems.

In this paper, a new model of the frequency dependence of the double-barrier THz rectifier is presented. The new structure is of interest because it can be realized by CMOS image sensor technology. Its application in a complex field such as that of THz receivers requires the availability of an analytical model, which is reliable and able to highlight the dependence on the parameters of the physical structure. The model is based on the hydrodynamic semiconductor equations, solved in the small signal approximation.

We present a new technique which allows the growth of silicon nanostructures at low temperature, in different forms. The growth takes place with the presence of a gaseous silicon precursor and a metal catalyst, once the eutectic temperature is overcome. The technique we present is based on heating limited to the metal nanoparticles, by irradiation of Microwaves. The so called nano-susceptors absorbs energy that produces large local increase of temperature. Only the metal nanoparticles reach high temperatures.

The occurrence of voltage noise in digital circuits has been typically associated to logic errors. The noise exposure of nano-scale circuits, associated to process variability, makes it interesting to explore the impact of input noise voltage pulses on the static power of idle logic cells, even if the logic operation is not compromised. This work proposes a simple yet effective characterization model to characterize the resulting shift in static energy consumption.

Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed.