Ricerc@Sapienza

We propose here an implementation of 2D hierarchical clustering tailored for power constrained and low-precision hardware. In many application fields such as smart sensor networks, having low computational capacity is mandatory for energy saving purposes. In this context, we aim to deploy a specific constrained hardware solution, using a parallel architecture with a low number of bits. The effectiveness of the proposed approach is corroborated by testing it on well-known 2D clustering datasets.

The Frisch-Waugh-Lovell (FWL) Recursive Least Squares (RLS) algorithm has been recently proposed as an RLS algorithm with lower computational cost and better numerical properties. We propose a VHDL implementation that has been successfully implemented on a Xilinx Virtex-7 FPGA. The FWL RLS algorithm has a complexity of L2 + O(L) products, instead of 1.5L2 O(L) as in conventional RLS algorithms. Because it removes all matrix operations, separating an L input vector problem into L separate scalar problems, it is stable and often faster in fixed-point arithmetic than conventional RLS.