low-power

An energy-aware hardware implementation of 2D hierarchical clustering

We propose here an implementation of 2D hierarchical clustering tailored for power constrained and low-precision hardware. In many application fields such as smart sensor networks, having low computational capacity is mandatory for energy saving purposes. In this context, we aim to deploy a specific constrained hardware solution, using a parallel architecture with a low number of bits. The effectiveness of the proposed approach is corroborated by testing it on well-known 2D clustering datasets.

A parallel hardware implementation for 2D hierarchical clustering based on fuzzy logic

In this paper we propose a novel hardware implementation for a bidimensional unconstrained hierarchical clustering method, based on fuzzy logic and membership functions. Unlike classical clustering approaches, our work is based on an advanced algorithm that shows an intrinsic parallelism. Such parallelism can be exploited to design an efficient hardware implementation suitable for low-resources, low-power and highcomputational demanding applications like smart-sensors and IoT devices. We validated our design by an extensive simulation campaign on well known 2D clustering datasets.

Area-efficient low-power bandpass Gm-C filter for epileptic seizure detection in 130nm CMOS

A low-power 6th-order Butterworth bandpass filter has been designed for the front-end of an integrated neural recording system. The passband has been set to 250-500Hz to allow recording the fast ripple (FR) associated with epileptic seizure onset and filter out all other undesired components of the neural signals. The filter is composed of 3 Gm-C biquad stages. Low-power operation is achieved by biasing the MOS devices in the sub-threshold region, and using a dual power supply of ±0.5V.

Power-efficient dynamic-biased CCII

In this work a dynamic biasing circuit for current conveyor (CCII) applications is proposed and discussed with circuitry details. This solution, applied for the first time to current-mode circuits, allows to decrease the steady state power consumption of the considered circuit, minimally affecting its performance. The dynamic biasing solution here conceived is able to sense the input signal providing an extra current to the CCII only when an input voltage variation occurs.

Low power switched-resistor band-pass filter for neural recording channels in 130nm CMOS

In this work, we present a low-power 2nd order band-pass filter for neural recording applications. The central frequency of the passband is set to 375Hz and the quality factor to 5 to properly process the neural signals related to the onset of epileptic seizure, and to strongly attenuate all the out of band biological signals and electrical disturbances. The biquad filter is based on a fully differential Tow Thomas architecture in which high-valued resistors are implemented through switched high-resistivity polysilicon resistors.

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