Ricerc@Sapienza

Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution to maximize the pipeline utilization, when it comes to executing parallel applications, as different threads operate different instruction processing phases in the same cycle. In this study, we expand the target applications of an IMT microarchitecture by introducing an efficient yet handy special-purpose mathematics engine, operating on local scratchpad memories that give low latency and wide data-bus access.

FPGA-synthesizable soft-processor cores are commonly used in many digital system applications with low medium production volume, to control heterogeneous dedicated computational units and I/O units. In such contexts, the inherently multi-tasking nature of the processor operation demands for a cost-effective and energy-efficient multi-threaded execution, either as multi-core architecture or multi-threaded single-core. This work presents an experimental exploration of microarchitecture design solutions for multi-threaded soft processor core implementations on FPGA.

Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running multiple control threads. Such architecture scheme fits one of the main target application domain of the RISC-V instruction set. We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for IoT applications. The latter feature is a novel contribution in this application domain.

Radiation hardening for coping with cosmic-ray-induced faults in electronic equipment has always been a central topic of hardware/software development for aerospace missions. This work presents the design, verification and validation of an 8-bit space-rated RISC MCU FPGA soft-core, featuring hardware architecture and instruction set architecture full compliance with Microchip® PICmicro Midrange MCU.

In this article, we describe the context in which an international race towards Exascale computing has started. We cover the political and economic context and make a review of the recent history in high performance computing (HPC) architectures, with special emphasis on the recently announced European initiatives to reach Exascale computing in Europe. We conclude by describing current challenges and trends.