Ricerc@Sapienza

Nowadays, computer architectures rely on multi-core processors, with out-of-order and speculative engines, often flanked by external elements such as GPUs and dedicated accelerators whose interoperability outlines the contemporary concept of heterogeneous systems. For its part, software has its own progression, most of the time determined by the currently rising topics (e.g. AI, Big Data) and the new hardware facilities which lead to new programming environments targeting better hw-sw cooperation. In such a complex world, understanding software structure and carefully analyzing its activity at runtime is a fundamental task to evaluate security, correctness, or efficiency issues. Instrumentation is the most employed execution analysis technique and operates at several abstraction levels according to the selected strategy. To enforce instrumentation, modern processors are provided with Performance Monitor Units (PMUs), special support for probing the cpu circuitry activity with a very negligible overhead also providing information that software instrumentation may just infer or never access.
The objective of this research project is to design on-line profiling methods, and their actual implementation, with the main aim of optimizing runtime monitoring execution of general applications and providing a dedicated tool for hardware contention resource among active workloads on system. Among all, in order to purse the portability of our solution among different architecture, despite the high PMUs heterogeneity, we will take advantage of the well-known Top-Down Analysis that defines a general methodology to study hardware response to particular code execution.
During this project, the hardware monitoring support will be seen as a vertical attribute of the profiler framework. Moreover, a strong focus will be posed on reducing perturbation and overhead generated by profiler activity to improve the effectiveness of any possible further data exploitation stages.