Salta al contenuto principale

Ricerc@Sapienza

Home
Login

Home
optimisation
simple logical effort optimisation
Risultati ricerca pubblicazioni

Risultati ricerca pubblicazioni

Torna alla Home Page delle pubblicazioni

Optimal pipeline stage balancing in the presence of large isolated interconnect delay

pubblicato su: ELECTRONICS LETTERS - 2017

Olivieri Mauro, Menichelli Francesco, Mastrandrea Antonio

CATALOGO IRIS SAPIENZA

Anno

2017 (1) Apply 2017 filter

Tipo pubblicazione

01 Pubblicazione su rivista (1) Apply 01 Pubblicazione su rivista filter

Rivista

ELECTRONICS LETTERS (1) Apply ELECTRONICS LETTERS filter

Book

Keywords

(-) Remove optimisation filter optimisation
(-) Remove simple logical effort optimisation filter simple logical effort optimisation
combinational circuits (1) Apply combinational circuits filter
combinational logic data-path (1) Apply combinational logic data-path filter
digital processing (1) Apply digital processing filter
fan-out delay overhead (1) Apply fan-out delay overhead filter
heuristic approach (1) Apply heuristic approach filter
Integrated circuit interconnections (1) Apply Integrated circuit interconnections filter
large isolated interconnect delay (1) Apply large isolated interconnect delay filter
optimal pipeline stage balancing (1) Apply optimal pipeline stage balancing filter
pipeline processing (1) Apply pipeline processing filter
pipeline stage delay imbalance (1) Apply pipeline stage delay imbalance filter

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma