Antonio Mastrandrea

Pubblicazioni

Titolo Pubblicato in Anno
A Simple Microwave Imaging System for Food Product Inspection through a Symmetry-Based Microwave Imaging Approach SENSORS 2024
Measurements of exhaled CO2 through a novel telemedicine tool Lecture Notes in Electrical Engineering 2024
3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool Sensors and Microsystems Proceedings of AISEM 2022 2023
Contextual bandits algorithms for reconfigurable hardware accelerators Lecture Notes in Electrical Engineering 2023
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor 2023
Improving SET fault resilience by exploiting buffered DMR microarchitecture SIE 2022. Proceedings of SIE 2022 2023
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy SIE 2023: Proceedings of SIE 2023 2023
Fault-tolerant hardware acceleration for high-performance edge-computing nodes ELECTRONICS 2023
Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) 2023
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration Conference on Ph.D Research in Microelectronics and Electronics (PRIME) 2022
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS 2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors IEEE ACCESS 2022
Characterization of Disposable Facemasks for COVID-19 Through Colorimetric Analysis NanoInnovation 21/09/2021 - 24/09/2021 Faculty of Civil and Industrial Engineering, Sapienza University of Rome, Rome, Italy 2022
Customizable vector acceleration in extreme-edge computing: A risc-v software/hardware architecture study on VGG-16 implementation ELECTRONICS 2021
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores IEEE MICRO 2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design 34rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021 2021
Quality aware selective ECC for approximate DRAM Applications in Electronics Pervading Industry, Environment and Society APPLEPIES 2019 2020
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer Lecture Notes in Electrical Engineering 2020
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor Lecture Notes in Electrical Engineering 2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020 2020

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