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antonio.mastrandrea@uniroma1.it
Antonio Mastrandrea
Personale Tecnico Amministrativo
Struttura:
DIPARTIMENTO DI SCIENZE STATISTICHE
E-mail:
antonio.mastrandrea@uniroma1.it
Pagina istituzionale corsi di laurea
Curriculum Sapienza
Pubblicazioni
Titolo
Pubblicato in
Anno
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors
IEEE ACCESS
2022
Characterization of Disposable Facemasks for COVID-19 Through Colorimetric Analysis
NanoInnovation 21/09/2021 - 24/09/2021 Faculty of Civil and Industrial Engineering, Sapienza University of Rome, Rome, Italy
2022
Customizable vector acceleration in extreme-edge computing: A risc-v software/hardware architecture study on VGG-16 implementation
ELECTRONICS
2021
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores
IEEE MICRO
2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
34rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
2021
Quality aware selective ECC for approximate DRAM
Applications in Electronics Pervading Industry, Environment and Society APPLEPIES 2019
2020
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer
Lecture Notes in Electrical Engineering
2020
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
Lecture Notes in Electrical Engineering
2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020
2020
An fpga-based risc-v computer architecture orbital laboratory on a pocketqube satellite
Advances in the Astronautical Sciences
2020
Full system emulation of approximate memory platforms with AppropinQuo
JOURNAL OF LOW POWER ELECTRONICS
2019
Approximate memory support for Linux early allocators in ARM architectures
Applications in Electronics Pervading Industry, Environment and Society
2019
Synthesis time reconfigurable floating point unit for transprecision computing
Applications in Electronics Pervading Industry, Environment and Society
2019
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
Lecture Notes in Electrical Engineering
2019
Dosimetric characterization of an irradiation set-up for electronic components testing at the TOP-IMPLART proton linear accelerator
Proceedings of RADECS 2019, Montpellier 17-20 September 2019
2019
Quality aware approximate memory in RISC-V Linux Kernel
PRIME 2019 - 15th Conference on Ph.D. Research in Microelectronics and Electronics, Proceedings
2019
A PULP-based Parallel Power Controller for Future Exascale Systems
2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
2019
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique
Lecture Notes in Electrical Engineering
2018
Impact of approximate memory data allocation on a H.264 software video encoder
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
2018
AppropinQuo: a platform emulator for exploring the approximate memory design space
2018 New Generation of CAS (NGCAS)
2018
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