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valerio.spinogatti@uniroma1.it
Valerio Spinogatti
Lavoratore autonomo
Struttura:
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI
E-mail:
valerio.spinogatti@uniroma1.it
Pagina istituzionale corsi di laurea
Curriculum Sapienza
Pubblicazioni
Titolo
Pubblicato in
Anno
Body biasing techniques for dynamic comparators: a systematic survey
ELECTRONICS
2024
A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme
2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
2024
Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage
2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
2024
A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
2023
High-accuracy low-cost generalized complex pruned Volterra models for nonlinear calibration
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS
2023
A novel ultra-low voltage fully synthesizable comparator exploiting NAND gates
PRIME 23. 18th International conference on Ph.D. research in microelectronics and electronics
2023
Robust body biasing techniques for dynamic comparators
PRIME 23. 18th International conference on Ph.D. research in microelectronics and electronics
2023
A 2.5 GHz, 0.6 V body driven dynamic comparator exploiting charge pump based dynamic biasing
PRIME 23. 18th International conference on Ph.D. research in microelectronics and electronics
2023
An improved strong arm comparator with integrated static preamplifier
IEEE ACCESS
2023
A 17 GHz inductorless low-pass filter based on a quasi-Sallen–Key approach
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
2023
A class-AB linear transconductor with enhanced linearity
AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
2021
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