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abdallah.cheikh@uniroma1.it
Abdallah Cheikh
Assegnista di ricerca
Struttura:
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI
E-mail:
abdallah.cheikh@uniroma1.it
Pagina istituzionale corsi di laurea
Curriculum Sapienza
Pubblicazioni
Titolo
Pubblicato in
Anno
Contextual bandits algorithms for reconfigurable hardware accelerators
Lecture Notes in Electrical Engineering
2023
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor
2023
Improving SET fault resilience by exploiting buffered DMR microarchitecture
SIE 2022. Proceedings of SIE 2022
2023
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy
SIE 2023: Proceedings of SIE 2023
2023
Fault-tolerant hardware acceleration for high-performance edge-computing nodes
ELECTRONICS
2023
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration
Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
2022
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors
IEEE ACCESS
2022
Customizable vector acceleration in extreme-edge computing: A risc-v software/hardware architecture study on VGG-16 implementation
ELECTRONICS
2021
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores
IEEE MICRO
2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
34rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021
2021
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer
Lecture Notes in Electrical Engineering
2020
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
Lecture Notes in Electrical Engineering
2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020
2020
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
Lecture Notes in Electrical Engineering
2019
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores
Proceedings - 2017 1st New Generation of CAS, NGCAS 2017
2017
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