Abdallah Cheikh | Ricerc@Sapienza

Pubblicazioni

Titolo	Pubblicato in	Anno
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme	IEEE TRANSACTIONS ON COMPUTERS	2024
AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs	Proceedings of the International Joint Conference on Neural Networks	2024
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems	IEEE ACCESS	2024
A RISC-V fault-tolerant soft-processor based on full/partial heterogeneous dual-core protection	IEEE ACCESS	2024
Heterogeneous tightly-coupled dual core architecture against single event effects	Lecture Notes in Electrical Engineering	2024
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design	Lecture Notes in Electrical Engineering	2024
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach	Lecture Notes in Electrical Engineering	2024
Contextual bandits algorithms for reconfigurable hardware accelerators	Lecture Notes in Electrical Engineering	2023
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor		2023
Improving SET fault resilience by exploiting buffered DMR microarchitecture	SIE 2022. Proceedings of SIE 2022	2023
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy	SIE 2023: Proceedings of SIE 2023	2023
Fault-tolerant hardware acceleration for high-performance edge-computing nodes	ELECTRONICS	2023
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration	Conference on Ph.D Research in Microelectronics and Electronics (PRIME)	2022
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core	JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS	2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors	IEEE ACCESS	2022
Customizable vector acceleration in extreme-edge computing: A risc-v software/hardware architecture study on VGG-16 implementation	ELECTRONICS	2021
Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores	IEEE MICRO	2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design	34rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021	2021
A RISC-V fault-tolerant microcontroller core architecture based on a hardware thread full/partial protection and a thread-controlled Watch-dog timer	Lecture Notes in Electrical Engineering	2020
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor	Lecture Notes in Electrical Engineering	2020