Abdallah Cheikh

Pubblicazioni

Titolo Pubblicato in Anno
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020 2020
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes Lecture Notes in Electrical Engineering 2019
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores Proceedings - 2017 1st New Generation of CAS, NGCAS 2017 2017

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma