Riccardo Della Sala

Pubblicazioni

Titolo Pubblicato in Anno
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications IEEE ACCESS 2024
An Ultra Low Voltage Physical Unclonable Function Exploiting Body-Driven Feedbacks SIE 23: 54th Annual Meeting of the Associazione Società Italiana di Elettronica 2024
A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier IEEE ACCESS 2024
Body biasing techniques for dynamic comparators: a systematic survey ELECTRONICS 2024
On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation IEEE ACCESS 2024
A 0.3 V OTA with enhanced CMRR and high robustness to PVT variations JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS 2024
A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs PRIME 24: 19th International Conference on Ph.D. Research in Microelectronics and Electronics 2024
Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage 2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024 2024
An ultra-low-voltage approach to accurately set the quiescent current of digital standard cells used for analog design and its application on an inverter-based operational transconductance amplifier JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS 2024
On Enhancing the Throughput of the Latched Ring Oscillator TRNG on FPGA SpringerLink 2024
Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS 2024
A 0.3 V Three-Stage Body-Driven OTA Proceedings of SIE 2022 Annual Meeting of the Italian Electronics Society 2023
A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C ELECTRONICS 2023
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations IEEE ACCESS 2023
A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow APPLIED SCIENCES 2023
A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS 2023
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2023
Standard-cell-based comparators for ultra-low voltage application. Analysis and Comparisons CHIPS 2023
A novel ultra-low voltage fully synthesizable comparator exploiting NAND gates PRIME 23. 18th International conference on Ph.D. research in microelectronics and electronics 2023
Robust body biasing techniques for dynamic comparators PRIME 23. 18th International conference on Ph.D. research in microelectronics and electronics 2023

ERC

  • PE6_1
  • PE6_2
  • PE6_3
  • PE6_5

KET

  • Rapid Prototyping e Additive Manufacturing
  • Big data & computing
  • Micro/nano electronics & photonics

Interessi di ricerca

His main research interests include the design and development of analog and digital PUFs for hardware security and the development and validation of TRNGs.
Furthermore, in the context of analog design, his research activity is focused on ultra-low voltage ultra-low power topology for IOT and biomedical applications.

Keywords

operational transconductance amplifier
Low power architecture
cyber-physical security
FPGA

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma