Alessandro Trifiletti

Pubblicazioni

Titolo Pubblicato in Anno
Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2018
Secure double rate registers as an RTL countermeasure against power analysis attacks IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018
A 0.6 V class-AB rail-to-rail CMOS OTA exploiting threshold lowering ELECTRONICS LETTERS 2018
A topology of fully differential class-AB symmetrical OTA with improved CMRR IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS 2018
A 10 GHz inductorless active SiGe HBT lowpass filter INTERNATIONAL JOURNAL OF RF AND MICROWAVE COMPUTER-AIDED ENGINEERING 2018
TEL logic style as a countermeasure against side-channel attacks: secure cells library in 65nm CMOS and experimental results IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS 2018
Design of broadband high dynamic-range fiber optic links JOURNAL OF OPTICAL COMMUNICATIONS 2018
Machine learning techniques for frequency sharing in a cognitive radar 2018 IEEE Radar Conference, RadarConf 2018 2018
Secure implementation of TEL-compatible flip-flops using a standard-cell approach Proceedings - IEEE International Symposium on Circuits and Systems 2018
Streamline calibration modelling for a comprehensive design of ATI-based digitizers MEASUREMENT 2018
New models for the calibration of four-channel time-interleaved ADCs using filter banks IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS 2018
Parallel and hierarchical architectures of 4-channel MFP digitizer Journal of Physics: Conference Series 2018
A 2-channel digitizer based on MFP strategy Journal of Physics: Conference Series 2018
Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2017
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2017
0.9-V class-AB Miller OTA in 0.35-μm CMOS with threshold-lowered non-tailed differential pair IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS 2017
A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4s metric IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS 2017
The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2017
Fully differential class-AB OTA with improved CMRR JOURNAL OF CIRCUITS, SYSTEMS, AND COMPUTERS 2017
Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2017

Progetti di Ricerca

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma