Alessandro Trifiletti

Pubblicazioni

Titolo Pubblicato in Anno
Streamline calibration modelling for a comprehensive design of ATI-based digitizers MEASUREMENT 2018
New models for the calibration of four-channel time-interleaved ADCs using filter banks IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS 2018
Parallel and hierarchical architectures of 4-channel MFP digitizer Journal of Physics: Conference Series 2018
A 2-channel digitizer based on MFP strategy Journal of Physics: Conference Series 2018
Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2017
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2017
0.9-V class-AB Miller OTA in 0.35-μm CMOS with threshold-lowered non-tailed differential pair IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS 2017
A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4s metric IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS 2017
The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2017
Fully differential class-AB OTA with improved CMRR JOURNAL OF CIRCUITS, SYSTEMS, AND COMPUTERS 2017
Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2017
Novel measurements setup for attacks exploiting static power using DC pico-ammeter 2017 European Conference on Circuit Theory and Design (ECCTD) 2017
VHDL implementation of FWL RLS algorithm 2017 European Conference on Circuit Theory and Design (ECCTD) 2017
Fully integrable current-mode feedback suppressor as an analog countermeasure against CPA attacks in 40nm CMOS technology PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings 2017
On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks 2017 European Conference on Circuit Theory and Design, ECCTD 2017 2017
A fully-differential class-AB OTA with CMRR improved by local feedback 2017 European Conference on Circuit Theory and Design, ECCTD 2017 2017
Class-AB current conveyors based on the FVF 2017 European Conference on Circuit Theory and Design, ECCTD 2017 2017
Power-efficient dynamic-biased CCII 2017 European Conference on Circuit Theory and Design, ECCTD 2017 2017
Reconfigurable low voltage inverter-based sample-and-hold amplifier PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings 2017
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric Proceedings - IEEE International Symposium on Circuits and Systems 2017

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma