Marco Angioli | Ricerc@Sapienza

Pubblicazioni

Titolo	Pubblicato in	Anno
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme	IEEE TRANSACTIONS ON COMPUTERS	2024
AeneasHDC: an automatic framework for deploying hyperdimensional computing models on FPGAs	Proceedings of the International Joint Conference on Neural Networks	2024
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems	IEEE ACCESS	2024
Heterogeneous tightly-coupled dual core architecture against single event effects	Lecture Notes in Electrical Engineering	2024
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design	Lecture Notes in Electrical Engineering	2024
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach	Lecture Notes in Electrical Engineering	2024
Contextual bandits algorithms for reconfigurable hardware accelerators	Lecture Notes in Electrical Engineering	2023
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor		2023
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy	SIE 2023: Proceedings of SIE 2023	2023
Fault-tolerant hardware acceleration for high-performance edge-computing nodes	ELECTRONICS	2023
Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor	2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)	2023