Pubblicazioni

The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes

2019 - Lecture Notes in Electrical Engineering
Cheikh, A.; Cerutti, G.; Mastrandrea, A.; Menichelli, F.; Olivieri, M.

Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores

2017 - Proceedings - 2017 1st New Generation of CAS, NGCAS 2017
Olivieri, Mauro; Cheikh, Abdallah; Cerutti, Gianmarco; Mastrandrea, Antonio; Menichelli, Francesco

© Università degli Studi di Roma "La Sapienza" - Piazzale Aldo Moro 5, 00185 Roma