Ricerc@Sapienza

Scaling the Metal Oxide Semiconductor (MOS) transistor dimensions down to the nanoscale and increasing the density of bits in an integrated Complementary MOS (CMOS) chip are mainly led by an extraordinary improvement of chip performance and the consequent economic revenues for semiconductor industries. Unfortunately, scaling the MOS size also causes a variety of drawbacks, degrading the transistor and circuit reliability. These are mainly due to local increase of the electric field in the transistor, creation of new traps in the gate oxide and transient phenomena related to capture and release of free carriers in the defect sites. The time-to-failure is the lifetime before a certain percentage degradation of the electrical behaviour of the transistor. It is a key feature of the technology node monitored by the semiconductor industries before releasing the product to the market. Among others, the instability of the threshold voltage is one of the most critical effect of the transistor reliability degradation, since alters the switch-on and switch-off conditions of the transistor. In this project, we propose to make systematic measurements of the threshold voltage instability during and after stress and to develop an analytical model able to explain the physical mechanisms involved and the role of the different types of traps. The ultimate goal of the project is to predict the transistor time-to-failure. Samples will be stressed at various temperatures and voltages, after which the threshold voltage will be measured. However, during the delay time after the end of the stress before the measurement a partial recovery of the threshold voltage occurs, which alters the value of the measurement, thus introducing an error in the calculation of the time-to-failure. An accurate model also of the recovery will be necessary to correct that error and to extrapolate the true value of the time-to-failure of the transistor.