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antonio.mastrandrea@uniroma1.it
Antonio Mastrandrea
Personale Tecnico Amministrativo
Struttura:
DIPARTIMENTO DI SCIENZE STATISTICHE
E-mail:
antonio.mastrandrea@uniroma1.it
Pagina istituzionale corsi di laurea
Curriculum Sapienza
Pubblicazioni
Titolo
Pubblicato in
Anno
Characterizing noise pulse effects on the power consumption of idle digital cells
Proceedings - IEEE International Symposium on Circuits and Systems (ISCAS)
2018
A space-rated soft IP-core compatible with the PIC®hardware architecture and instruction set
4th IAA Conference on University Satellite Missions and CubeSat Workshop
2018
Optimal pipeline stage balancing in the presence of large isolated interconnect delay
ELECTRONICS LETTERS
2017
An emulator for approximate memory platforms based on QEmu
Applications in Electronics Pervading Industry, Environment and Society
2017
Introducing approximate memory support in Linux Kernel
PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings
2017
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores
Proceedings - 2017 1st New Generation of CAS, NGCAS 2017
2017
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops
MICROELECTRONICS RELIABILITY
2015
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions
2015 4th International Conference on Reliability, Infocom Technologies and Optimization: Trends and Future Directions, ICRITO 2015
2015
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