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giuseppe.scotti@uniroma1.it
Giuseppe Scotti
Professore Associato
Struttura:
DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE, ELETTRONICA E TELECOMUNICAZIONI
E-mail:
giuseppe.scotti@uniroma1.it
Pagina istituzionale corsi di laurea
Curriculum Sapienza
Pubblicazioni
Titolo
Pubblicato in
Anno
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications
IEEE ACCESS
2024
An Ultra Low Voltage Physical Unclonable Function Exploiting Body-Driven Feedbacks
SIE 23: 54th Annual Meeting of the Associazione Società Italiana di Elettronica
2024
A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier
IEEE ACCESS
2024
On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation
IEEE ACCESS
2024
A 0.3 V OTA with enhanced CMRR and high robustness to PVT variations
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
2024
A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs
PRIME 24: 19th International Conference on Ph.D. Research in Microelectronics and Electronics
2024
A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme
2024 19th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2024
2024
A 0.064 mm2 16-channel in-pixel neural front end with improved system common-mode rejection exploiting a current-mode summing approach
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
2024
An ultra-low-voltage approach to accurately set the quiescent current of digital standard cells used for analog design and its application on an inverter-based operational transconductance amplifier
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
2024
On Enhancing the Throughput of the Latched Ring Oscillator TRNG on FPGA
SpringerLink
2024
Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS
2024
A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS
2023
A 0.3 V Three-Stage Body-Driven OTA
Proceedings of SIE 2022 Annual Meeting of the Italian Electronics Society
2023
A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C
ELECTRONICS
2023
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations
IEEE ACCESS
2023
A High Performance 0.3 V Standard-Cell-Based OTA Suitable for Automatic Layout Flow
APPLIED SCIENCES
2023
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
2023
Standard-cell-based comparators for ultra-low voltage application. Analysis and Comparisons
CHIPS
2023
High-accuracy low-cost generalized complex pruned Volterra models for nonlinear calibration
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS
2023
Wide-Band Shared LNA for Large Scale Neural Recording Applications
SMACD 23: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
2023
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Progetti di Ricerca
Progetto di circuiti integrati CMOS a bassissima tensione di alimentazione e a bassissimo consumo di potenza per sistemi biomedicali "impiantati" con particolare riferimento all'elaborazione dei segnali neurali e alla neuro-robotica.
Studio degli attacchi "power analysis" basati sulla misura del consumo di potenza statico di dispositivi crittografici implementati con tecnologie CMOS nanometriche e sviluppo di contromisure atte a garantire la sicurezza rispetto ai diversi tipi di...
Progetto di circuiti integrati a bassa tensione di alimentazione e a basso consumo di potenza per applicazioni di neural recording e brain machine interfaces sfruttando le potenzialità delle recenti tecnologie CMOS nanometriche e il funzionamento so...
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