Pubblicazioni

Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme

2024 - IEEE TRANSACTIONS ON COMPUTERS
Angioli, Marco; Barbirotta, Marcello; Cheikh, Abdallah; Mastrandrea, Antonio; Menichelli, Francesco; Jamili, Saeid; Olivieri, Mauro

Adaptive Model-based Scheduling in Software Transactional Memory

2020 - IEEE TRANSACTIONS ON COMPUTERS
Di Sanzo, Pierangelo; Pellegrini, Alessandro; Sannicandro, Marco; Ciciani, Bruno; Quaglia, Francesco

Schedulability Analysis of Conditional Parallel Task Graphs in Multicore Systems

2017 - IEEE TRANSACTIONS ON COMPUTERS
Melani, Alessandra; Bertogna, Marko; Bonifaci, Vincenzo; MARCHETTI SPACCAMELA, Alberto; Buttazzo, Giorgio

Exact Response Time Analysis for Fixed Priority Memory-Processor Co-Scheduling

2017 - IEEE TRANSACTIONS ON COMPUTERS
Melani, Alessandra; Bertogna, Marko; Davis, Robert I.; Bonifaci, Vincenzo; Marchetti Spaccamela, Alberto; Buttazzo, Giorgio

The size of BDDs and other data structures in temporal logics model checking

2016 - IEEE TRANSACTIONS ON COMPUTERS
Ferrara, Andrea; Liberatore, Paolo; Schaerf, Marco

Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput

2016 - IEEE TRANSACTIONS ON COMPUTERS
Pontarelli, S; Reviriego, P; Maestro, Ja

Efficient notification ordering for geo-distributed pub/sub systems

2015 - IEEE TRANSACTIONS ON COMPUTERS
Baldoni, Roberto; Bonomi, Silvia; Platania, Marco; Querzoni, Leonardo

Low delay single symbol error correction codes based on reed solomon codes

2015 - IEEE TRANSACTIONS ON COMPUTERS
Pontarelli, S; Reviriego, P; Ottavi, M; Maestro, Ja

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