Giuseppe Scotti | Ricerc@Sapienza

Pubblicazioni

Titolo	Pubblicato in	Anno
A very-olw-voltage frequency divider in folded MOS current mode logic with complementary n- and p-type flip-flops	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS	2021
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML	ISCAS 2021 IEEE International Symposium on Circuits and Systems	2021
0.5-V frequency dividers in folded MCML exploiting forward body bias: analysis and comparison	ELECTRONICS	2021
SC-DDPL as a countermeasure against static power side-channel attacks	CRYPTOGRAPHY	2021
A novel OTA architecture exploiting current gain stages to boost bandwidth and slew-rate	ELECTRONICS	2021
Distributed switched-resistor approach for high-Q biquad filters	AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS	2021
A detailed model of the switched-resistor technique	IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS	2021
A novel ultra-compact FPGA PUF: The DD-PUF	CRYPTOGRAPHY	2021
An E-band variable gain amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology	FREQUENZ	2021
A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route	JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS	2021
0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control	JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS	2021
A novel 0.5 v MCML D-flip-flop topology exploiting forward body bias threshold lowering	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS	2020
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS	2020
10-GHz fully differential Sallen–Key lowpass biquad filters in 55nm SiGe BICMOS technology	ELECTRONICS	2020
Delay models and design guidelines for MCML gates with resistor or PMOS load	MICROELECTRONICS JOURNAL	2020
Low power switched-resistor band-pass filter for neural recording channels in 130nm CMOS	HELIYON	2020
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response	INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS	2020
A power efficient frequency divider with 55 GHz self-oscillating frequency in SiGe BiCMOS	ELECTRONICS	2020
A multi-folded MCML for ultra-low-voltage high-performance in deeply scaled CMOS	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS	2020
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS	2020

Progetti di Ricerca

Progetto di circuiti integrati CMOS a bassissima tensione di alimentazione e a bassissimo consumo di potenza per sistemi biomedicali "impiantati" con particolare riferimento all'elaborazione dei segnali neurali e alla neuro-robotica.
Studio degli attacchi "power analysis" basati sulla misura del consumo di potenza statico di dispositivi crittografici implementati con tecnologie CMOS nanometriche e sviluppo di contromisure atte a garantire la sicurezza rispetto ai diversi tipi di...
Progetto di circuiti integrati a bassa tensione di alimentazione e a basso consumo di potenza per applicazioni di neural recording e brain machine interfaces sfruttando le potenzialità delle recenti tecnologie CMOS nanometriche e il funzionamento so...