| Titolo |
Pubblicato in |
Anno |
| A multi-folded MCML for ultra-low-voltage high-performance in deeply scaled CMOS |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS |
2020 |
| SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS |
2020 |
| A novel 0.6V MCML D-latch topology exploiting dynamic body bias threshold lowering |
2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 |
2019 |
| Area-efficient low-power bandpass Gm-C filter for epileptic seizure detection in 130nm CMOS |
2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 |
2019 |
| Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS |
AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS |
2018 |
| Secure double rate registers as an RTL countermeasure against power analysis attacks |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
2018 |
| TEL logic style as a countermeasure against side-channel attacks: secure cells library in 65nm CMOS and experimental results |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS |
2018 |
| Secure implementation of TEL-compatible flip-flops using a standard-cell approach |
Proceedings - IEEE International Symposium on Circuits and Systems |
2018 |
| Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications |
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING |
2017 |
| Template attacks exploiting static power and application to CMOS lightweight crypto-hardware |
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
2017 |
| 0.9-V class-AB Miller OTA in 0.35-μm CMOS with threshold-lowered non-tailed differential pair |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS |
2017 |
| A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4s metric |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS |
2017 |
| Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
2017 |
| Novel measurements setup for attacks exploiting static power using DC pico-ammeter |
2017 European Conference on Circuit Theory and Design (ECCTD) |
2017 |
| Fully integrable current-mode feedback suppressor as an analog countermeasure against CPA attacks in 40nm CMOS technology |
PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings |
2017 |
| Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric |
Proceedings - IEEE International Symposium on Circuits and Systems |
2017 |
| Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications |
Progress in Cryptology - AFRICACRYPT 2017 |
2017 |
| CMOS Non-tailed differential pair |
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
2016 |
| On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology |
Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016 |
2016 |
| Implementation of the present-80 block cipher and analysis of its vulnerability to side channel attacks exploiting static power |
Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016 |
2016 |
